1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a construction of a static random access memory (hereinafter SRAM) cell and the fabrication method thereof.
2. Discussion of the Related Art
FIGS. 1 and 2 are plan views showing a layout of an SRAM cell according to the conventional art. As shown in FIG. 1, the conventional SRAM cell includes a plurality of active regions 93,94,96 and a polysilicon line 95, a polysilicon interconnection line I2 and a word line 97 formed on the active region 93,94. A transistor TPA is formed between the active region 96 and the polysilicon line 95. A first node (N1) is formed between the active region 93 and the polysilicon line 95, and a second node (N2) connects the active region 96 and a line I2. A transistor TPB is formed at the crossed point of the line I2 and the active region 93. The first node (N1) is formed at the point where the end of the line 95 crosses a mid portion of the active region 93. A transistor (T1) is formed where the active region 93 crosses the word line 97. At the active region 93 formed between the transistor TPB and the transistor T1 is an interconnection line I1 formed of an active layer material. One end of the word line 97 and the transistor (T2) are crossed in the active region 94. The transistors (TPA,TPB) are generally called drive transistors, and the transistors (T1,T2) are commonly called access transistors.
FIG. 2 is a plan view showing a layout of a split word line cell according to the conventional art. Referring to FIG. 2, the conventional SRAM cell having a split word line cell includes a plurality of active regions 90,91, polysilicon lines (N1,N2), and word lines (WL1,WL2) formed on the active regions 90,91. A transistor (T1) is formed where the line (N1) and the active region 90 crosses each other, and a transistor (T3) is formed where the word line (WL1) and the active region 90 crosses. A transistor (T4) is formed where the active region 91 and the word line (WL2) crosses each other.
In the SRAM cell of FIG. 2, local interconnection lines (I1,I2) are defined by a buried N+ line. A common drain of the transistors (T1,T3) and a gate of the transistor (T2) are electrically connected by the local interconnection line (I1). A common drain of the transistors (T4,T2) and a gate of the transistor (T1) are electrically connected by the local interconnection line (I2).
In the SRAM cell of FIG. 1, the active diffusion region 93 and the polysilicon line (I2) are used for the connection of the two nodes (N1,N2). The active diffusion region 93 and the polysilicon line (I2) each have different resistance values. Since the polysilicon and the diffusion region have each different resistances, and different line lengths, the SRAM cell is in an asymmetrical condition, which means that the local interconnection lines (I1,I2) of the conventional SRAM of FIG. 1 are defined as different layers. That is, one is an N+ diffusion layer, and the other is a polysilicon deposition layer. The two are composed of different materials. Thus, the resistances of the nodes (N1,N2) are different, which causes the cell to be more unstable and different currents to flow in the transistors (T1,T2). Accordingly, the cell is asymmetrical when the transistors are turned on.
Moreover, the conventional SRAM cell of FIG. 1 has a small cell size, but the cells are formed asymmetrically having a 45xc2x0 layout. Therefore, resolution is not good in a super high resolution illumination control (SHRINK), a lithography, or a phase inversion mask. Also, a metal design rule becomes tight. In addition, a plurality of active regions 93,94,96 (FIG. 1) in the SRAM cell increases the cell size and requires a plurality of contact holes to be formed during the wiring of ground lines. As a result, the ground resistance value of each drive transistor is made different.
In the conventional split word line cell shown in FIG. 2, each interconnection line (I1,I2) is defined as a diffusion layer formed of an identical material and an identical layer to improve the asymmetry problem of the SRAM cell shown in FIG. 1. However, since the SRAM cell has a plurality of active regions 90,91, the cell size occupies a large area and a plurality of contact holes must be formed when wiring a ground line, resulting in a different ground resistance values for each drive transistor.
Accordingly, the present invention is directed to a static random access memory cell that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an SRAM cell having a plurality of interconnection lines formed of substantially identical material and layer.
Another object of the present invention is to provide an SRAM cell having a single active region.
Another object of the present invention is to provide an SRAM cell having drive transistors with identical ground resistance.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an SRAM cell includes a semiconductor substrate, an active region formed in the semiconductor substrate, each gate line of first and second access transistors formed to cross the active region and parallel to each other, each gate line of first and second drive transistors formed between the gate lines of the first and second access transistors to be parallel to the gate lines thereof, a plurality of impurity regions formed in the active region at both sides of each four gate lines, and a ground power source line electrically connected to the impurity region corresponding to the space between the gate lines of the first and second drive transistors.
The active region is formed to be diagonally symmetrical in tiers, and the ground power source line is formed in parallel with the gates in a different layer.
In another aspect of the present invention, a method for fabricating the SRAM cell includes the steps of sequentially forming an insulating film and a first conductive layer on a semiconductor substrate; forming first through fourth gate lines crossed with an active region in parallel with each other by selectively etching the first conductive layer and the insulating film; forming first through fifth impurity regions by implanting an ion impurity into the active region using the four gate lines as a mask; forming a first contact hole so that the surface of the second impurity region formed between the first and second gate lines is exposed, a second contact hole so that the surface of the third gate line is exposed, a third contact hole so that the surface of the fourth impurity region formed between the third and fourth gate lines is exposed, and a fourth contact hole so that the surface of the second gate line is exposed, by forming a first insulating film on the semiconductor substrate including the active region and the four gate lines and selectively etching the first insulating film; forming a first conductive line filling the first and second contact holes and a second conductive line filling the third and fourth contact holes to be parallel with each other and to be perpendicular with the four gate lines after forming and patterning an undoped polysilicon layer on the first insulating film; implanting a conductive impurity into the space between first and second contact holes among the first conductive line and the space between the third and fourth contact holes among the second conductive lines; forming fifth and sixth contact holes to expose a predetermined portion where an impurity ion is not implanted among the first and second conductive lines and a seventh contact hole to expose the third impurity corresponding to the space between the second and third gate lines, by forming a second insulating film on the first insulating film including the first and second conductive lines and selectively etching the second insulating film; and forming first and second power source lines filled in the fifth and sixth contact holes and perpendicular to the first and second conductive lines to be parallel with each other, and a ground power source line filled in the seventh contact hole and parallel with the power source lines by forming and patterning a second conductive layer to fill the fifth through seventh contact holes formed on the second insulating film.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.